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2.5 v to 5.5 v, 250 a, 2-wire interface, dual voltage output, 8-/10-/12-bit dacs ad5337/ad5338/ad5339 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2007 analog devices, inc. all rights reserved. features ad5337 2 buffered 8-bit dacs in 8-lead msop ad5338, ad5338-1 2 buffered 10-bit dacs in 8-lead msop ad5339 2 buffered 12-bit dacs in 8-lead msop low power operation: 250 a @ 3 v, 300 a @ 5 v 2-wire (i 2 c-compatible) serial interface 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 80 na @ 3 v, 200 na @ 5 v 3 power-down modes double-buffered input logic output range: 0 v to v ref power-on reset to 0 v simultaneous update of outputs ( ldac function) software clear facility data readback facility on-chip rail-to-rail output buffer amplifiers temperature range: ?40c to +105c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control general description the ad5337/ad5338/ad5339 are dual 8-, 10-, and 12-bit buffered voltage output dacs, respectively. each part is housed in an 8-lead msop package and operates from a single 2.5 v to 5.5 v supply, consuming 250 a at 3 v. on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 v/s. a 2- wire serial interface operates at clock rates up to 400 khz. this interface is smbus compatible at v dd < 3.6 v. multiple devices can be placed on the same bus. the references for the two dacs are derived from one reference pin. the outputs of all dacs can be updated simultaneously using the software ldac function. the parts incorporate a power-on reset circuit to ensure that the dac outputs power up to 0 v and remain there until a valid write to the device takes place. a software clear function resets all input and dac registers to 0 v. a power-down feature reduces the current consumption of the devices to 200 na @ 5 v (80 na @ 3 v). the low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equip- ment. the power consumption is typically 1.5 mw at 5 v and 0.75 mw at 3 v, reducing to 1 w in power-down mode. functional block diagram scl buffer buffer ldac a0 sda gnd 03756-001 interface logic input register input register dac register dac register string dac a string dac b v out a v out b power-down logic ad5337/ad5338/ad5339 power-on reset refin v dd figure 1.
ad5337/ad5338/ad5339 rev. c | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac characteristics........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 13 theory of operation ...................................................................... 15 digital-to-analog converter section ...................................... 15 resistor string ............................................................................. 15 dac reference inputs ............................................................... 15 output amplifier........................................................................ 15 power-on reset ........................................................................... 15 serial interface ............................................................................ 16 write operation.......................................................................... 17 read operation........................................................................... 18 double-buffered interface ........................................................ 19 power-down modes .................................................................. 19 applications..................................................................................... 20 typical application circuit....................................................... 20 bipolar operation....................................................................... 20 multiple devices on one bus ................................................... 20 product as a digitally programmable window detector ..... 21 coarse and fine adjustment capabilities............................... 21 power supply decoupling ......................................................... 21 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 9/07rev. b to rev. c changes to features.......................................................................... 1 changes to table 4............................................................................ 7 changes to ordering guide .......................................................... 25 9/06rev. a to rev. b updated format..................................................................universal changes to figure 31...................................................................... 16 changes to table 6.......................................................................... 16 changes to table 10........................................................................ 23 changes to ordering guide .......................................................... 25 10/04rev. 0 to rev. a updated format..................................................................universal added ad5338-1................................................................universal changes to specifications.................................................................4 updated outline dimensions....................................................... 24 changes to ordering guide .......................................................... 24 11/03rev. 0: initial version
ad5337/ad5338/ad5339 rev. c | page 3 of 28 specifications v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. a grade 1 b grade 1 parameter 2 min typ max min typ max unit conditions/comments dc performance 3 , 4 ad5337 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.5 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5338 resolution 10 10 bits relative accuracy 0.5 4 0.5 2 lsb differential nonlinearity 0.05 0.5 0.05 0.50 lsb guaranteed monotonic by design over all codes ad5339 resolution 12 12 bits relative accuracy 2 16 2 8 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 0.4 3 % of fsr gain error 0.15 1 0.15 1 % of fsr lower deadband 20 60 20 60 mv lower deadband exists only if offset error is negative offset error drift 5 ?12 ?12 ppm of fsr/c gain error drift 5 ?5 ?5 ppm of fsr/c power supply rejection ratio 5 ?60 ?60 db ?v dd = 10% dc crosstalk 5 200 200 v r l = 2 k to gnd or v dd dac reference inputs 5 v ref input range 0.25 v dd 0.25 v dd v v ref input impedance 37 45 37 45 k normal operation >10 >10 m power-down mode reference feedthrough ?90 ?90 db frequency = 10 khz output characteristics 5 minimum output voltage 6 0.001 0.001 v measure of the minimum drive capabilities of the output amplifier maximum output voltage 6 v dd ? 0.001 v dd ? 0.001 v measure of the maximum drive capabilities of the output amplifier dc output impedance 0.5 0.5 short-circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 s coming out of power- down mode, v dd = 5 v 5 5 s coming out of power- down mode, v dd = 3 v
ad5337/ad5338/ad5339 rev. c | page 4 of 28 a grade 1 b grade 1 parameter 2 min typ max min typ max unit conditions/comments logic inputs (a0) 5 input current 1 1 a input low voltage (v il ) 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v input high voltage (v ih ) 2.4 2.4 v v dd = 5 v 10% 2.1 2.1 v v dd = 3 v 10% 2.0 2.0 v v dd = 2.5 v pin capacitance 3 3 pf logic inputs (scl, sda) 5 input high voltage (v ih ) 0.7 v dd v dd + 0.3 0.7 v dd v dd + 0.3 v smbus compatible at v dd < 3.6 v input low voltage (v il ) ?0.3 +0.3 v dd C0.3 +0.3 v dd v smbus compatible at v dd < 3.6 v input leakage current (i in ) 1 1 a input hysteresis (v hyst ) 0.05 v dd 0.05 v dd v input capacitance (c in ) 8 8 pf glitch rejection 50 50 ns input filtering suppresses noise spikes of less than 50 ns logic output (sda) 5 output low voltage (v ol ) 0.4 0.4 v i sink = 3 ma 0.6 0.6 v i sink = 6 ma three-state leakage current 1 1 a three-state output capacitance 8 8 pf power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 7 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 300 375 300 375 a v dd = 2.5 v to 3.6 v 250 350 250 350 a i dd (power-down mode) v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.2 1.0 0.2 1.0 a i dd = 4 a (max) during 0 readback on sda v dd = 2.5 v to 3.6 v 0.08 1.00 0.08 1.00 a i dd = 1.5 a (max) during 0 readback on sda 1 temperature range for a version and b vers ion: ?40c to +105c; typical at 25c. 2 see the terminology section for explan ations of the specific parameters. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduced code range: ad5337 (cod e 8 to code 248), ad5338, ad5338- 1 (code 28 to code 995), ad5339 (c ode 115 to code 3981). 5 guaranteed by design and characterization; not production tested. 6 for the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, v ref = v dd and offset plus gain error must be positive. 7 i dd specification is valid for all dac codes. interface in active. all dacs active an d excluding load currents.
ad5337/ad5338/ad5339 rev. c | page 5 of 28 ac characteristics v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. a version and b version 1 parameter 2 , 3 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5337 6 8 s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5338 7 9 s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5339 8 10 s 1/4 scale to 3/4 scale change (0x400 to 0xc00) slew rate 0.7 v/s major code transition glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 1 nv-s digital crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p total harmonic distortion ?70 db v ref = 2.5 v 0.1 v p-p, frequency = 10 khz 1 temperature range for a version and b vers ion: ?40c to +105c; typical at 25c. 2 guaranteed by design and characterization; not production tested. 3 see the terminology section for explan ations of the specific parameters.
ad5337/ad5338/ad5339 rev. c | page 6 of 28 timing characteristics v dd = 2.5 v to 5.5 v. all specifications t min to t max , unless otherwise noted. table 3. limit at t min , t max parameter a version and b version unit conditions/comments f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd, sta , start/repeated start condition hold time t 5 100 ns min t su, dat , data setup time t 6 1 0.9 s max t hd, dat , data hold time 0 s min t hd, dat , data hold time t 7 0.6 s min t su, sta , setup time for repeated start t 8 0.6 s min t su, sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda wh en receiving (cmos compatible) t 11 250 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1 c b 2 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line 1 a master device must provide a hold time of at least 300 ns for the sda signal (referred to v ih min of the scl signal) to bridge the undefined region of scls falling edge. 2 c b is the total capacitance of one bus line in pf; t r and t f measured between 0.3 v dd and 0.7 v dd . t 9 t 3 t 4 t 6 t 2 t 5 t 7 t 8 t 1 t 4 t 11 t 10 0 3756-002 sda scl start condition stop condition repeated start condition figure 2. 2-wire serial interface timing diagram
ad5337/ad5338/ad5339 rev. c | page 7 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7 v scl, sda to gnd ?0.3 v to v dd + 0.3 v a0 to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3 v v out a to v out b to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c msop package power dissipation (t j max ? t a ) ja ja thermal impedance 206c/w jc thermal impedance 44c/w lead temperature jedec industry standard soldering j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. transient currents of up to 100 ma do not cause scr latch-up. esd caution
ad5337/ad5338/ad5339 rev. c | page 8 of 28 pin configuration and fu nction descriptions 0 3756-003 v dd 1 v out a 2 v out b 3 refin 4 a0 8 scl 7 sda 6 gnd 5 top view (not to scale) ad5337/ ad5338/ ad5339 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 v dd power supply input. these parts can be operated from 2.5 v to 5.5 v, and the supply should be decoupled to gnd. 2 v out a buffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 3 v out b buffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 4 refin reference input pin for the two dacs. it has an input range from 0.25 v to v dd . 5 gnd ground reference point for all circuitry on the parts. 6 sda serial data line. this is used in conjunction with the scl line to clock data into or out of the 16-bit input shift register. sda is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 7 scl serial clock line. this is used in conjunction with the sd a line to clock data into or out of the 16-bit input shift register. clock rates of up to 400 kbps can be accommodated in the 2-wire interface. 8 a0 address input. sets the least sign ificant bit of the 7-bit slave address.
ad5337/ad5338/ad5339 rev. c | page 9 of 28 typical performance characteristics inl error (lsb) ?1.0 ?0.5 0 0.5 1.0 0 50 100 150 200 250 code t a = 25c v dd =5v 03756-006 figure 4. ad5337 typical inl plot ?3 ?2 ?1 0 1 2 3 inl error (lsb) 0 200 400 600 800 1000 code t a = 25c v dd =5v 03756-007 figure 5. ad5338 typical inl plot ?12 ?8 ?4 0 4 8 12 inl error (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code t a = 25c v dd =5v 03756-008 figure 6. ad5339 typical inl plot ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 dnl error (lsb) 0 50 100 150 200 250 code t a = 25c v dd =5v 03756-009 figure 7. ad5337 typical dnl plot ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 dnl error (lsb) 0 200 400 600 800 1000 code t a = 25c v dd =5v 03756-010 figure 8. ad5338 typical dnl plot dnl error (lsb) ?1.0 ?0.5 0 0.5 1.0 2000 1500 500 1000 0 2500 3000 3500 4000 code t a = 25c v dd =5v 03756-011 figure 9. ad5339 typical dnl plot
ad5337/ad5338/ad5339 rev. c | page 10 of 28 error (lsb) ?0.50 ?0.25 0 0.25 0.50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ref (v) t a = 25c v dd =5v max inl max dnl min dnl min inl 03756-012 figure 10. ad5337 inl and dnl error vs. v ref ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 error (lsb) temperature (c) 0 ?40 40 80 120 v dd =5v v ref =3v max inl max dnl min dnl min inl 03756-013 figure 11. ad5337 inl and dnl error vs. temperature error (%) ?1.0 ?0.5 0 0.5 1.0 temperature (c) 0 ?40 40 80 120 v dd =5v v ref =2v gain error offset error 03756-014 figure 12. ad5337 offset error and gain error vs. temperature ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 error (%) 0 0.1 0.2 23 01 45 v dd (v) 6 t a = 25c v ref =2v gain error offset error 03756-015 figure 13. offset error and gain error vs. v dd 0 1 2 3 4 5 v out (v) 23 01 45 sink/source current (ma) 6 5v source 3v source 5v sink 3v sink 03756-016 figure 14. v out source and sink current capability 0 50 100 150 200 250 300 zero scale full scale code t a = 25c v dd =5v v ref =2v 03756-017 i dd (a) figure 15. supply current vs. code
ad5337/ad5338/ad5339 rev. c | page 11 of 28 0 50 100 150 200 250 300 i dd (a) 3.5 4.0 2.5 3.0 4.5 5.0 5.5 v dd (v) +25c ?40c +105c 03756-018 figure 16. supply current vs. supply voltage 0 0.1 0.2 0.3 0.4 0.5 i dd (a) 3.5 4.0 2.5 3.0 4.5 5.0 5.5 v dd (v) +25c ?40c +105c 03756-019 figure 17. power-down current vs. supply voltage 0 50 100 150 200 250 i dd (a) 300 350 400 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v logic (v) t a = 25c v dd =5v v dd =3v increasing decreasing 03756-020 figure 18. supply current vs. logic input voltage for sda and scl voltage increasing and decreasing t a =25c v dd =5v v ref =5v v out a scl ch1 ch1 1v, ch2 5v, time base = 1s/div ch2 03756-021 figure 19. midscale settling (? to ? scale code change) t a = 25c v dd =5v v ref =2v v out a v dd ch1 ch1 2v, ch2 200mv, time base = 200s/div ch2 03756-022 figure 20. power-on reset to 0 v t a = 25c v dd =5v v ref =2v v out a scl ch1 ch1 500mv, ch2 5v, time base = 1s/div ch2 03756-023 figure 21. existing power-down to midscale
ad5337/ad5338/ad5339 rev. c | page 12 of 28 v dd =5v v dd =3v frequency i dd (a) 150 200 250 300 03756-024 figure 22. i dd histogram with v dd = 3 v and v dd = 5 v v out (v) 2.47 2.49 2.48 2.50 1s/div 03756-025 figure 23. ad5339 major code transition glitch energy ?60 ?50 ?40 ?30 ?20 ?10 0 10 db 1k 10k 10 100 100k 1m 10m frequency (hz) 03756-026 figure 24. multiplying bandwidth (small-signal frequency response) full-scale error (v) ?0.02 ?0.01 0 0.01 0.02 23 01 45 v ref (v) 6 t a = 25c v dd =5v 03756-027 figure 25. full-scale error vs. v ref 1mv/di v 50ns/div 03756-028 figure 26. dac-to -dac crosstalk
ad5337/ad5338/ad5339 rev. c | page 13 of 28 terminology relative accuracy (integral nonlinearity, inl) for the dac, relative accuracy, or integral nonlinearity (inl), is a measure, in lsbs, of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. typical inl vs. code plots can be seen in figure 4 , figure 5 , and figure 6 . differential nonlinearity (dnl) the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures mono- tonicity. this dac is guaranteed monotonic by design. typical dnl vs. code plots can be seen in figure 7 , figure 8 , and figure 9 . offset error a measure of the offset error of the dac and the output amplifier, expressed as a percentage of the full-scale range. gain error a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. offset error drift a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/c. gain error drift a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk the dc change in the output level of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in v. reference feedthrough the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. major code transition glitch energy the energy of the impulse injected into the analog output when the code in the dac register changes state. normally specified as the area of the glitch in nv-s, it is measured when the digital code is changed by 1 lsb at the major carry transition (011...11 to 100...00 or 100...00 to 011...11). digital feedthrough a measure of the impulse injected into the analog output of the dac from the digital input pins of the device when the dac output is not being updated. specified in nv-s and measured with a worst-case change on the digital input pins, such as changing from all 0s to all 1s or vice-versa. digital crosstalk the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s, or vice versa) in the input register of another dac. it is expressed in nv-s. dac-to-dac crosstalk the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s, or vice versa) with the ldac bit set low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. total harmonic distortion (thd) the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonic distortion present in the dac output. it is measured in db.
ad5337/ad5338/ad5339 rev. c | page 14 of 28 gain error plus offset error actual ideal dac code 03756-004 output voltage negative offset error deadband codes amplifier footroom (1mv) negative offset error figure 27. transfer functi on with negative offset gain error plus offset error dac code actual ideal 03756-005 output voltage positive offset figure 28. transfer function with positive offset
ad5337/ad5338/ad5339 rev. c | page 15 of 28 theory of operation the ad5337/ad5338/ad5339 are dual resistor string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. each part contains two output buffer amplifiers and is written to via a 2-wire serial interface. the dacs operate from single supplies of 2.5 v to 5.5 v, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/s. the two dacs share a single reference input pin. each dac has three programmable power-down modes that allow the output amplifier to be configured with either a 1 k load to ground, a 100 k load to ground, or as a high impedance three-state output. digital-to-analog converter section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer amplifier. the voltage at the refin pin provides the reference voltage for the dac. figure 29 shows a block diagram of the dac architecture. because the input coding to the dac is straight binary, the ideal output voltage is given by n ref out dv v 2 = where: d is the decimal equivalent of the binary code, which is loaded to the dac register 0 to 255 for ad5337 (8 bits) 0 to 1023 for ad5338 and ad5338-1 (10 bits) 0 to 4095 for ad5339 (12 bits) n is the dac resolution. input register refin output buffer amplifier v out a resistor string dac register 03756-029 figure 29. dac channel architecture resistor string the resistor string portion is shown in figure 30 . it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines the node at which the voltage is tapped off and fed into the output amplifier. the voltage is tapped off by closing one of the switches that connects the string to the amplifier. because the dac comprises a string of resistors, it is guaranteed to be monotonic. r r r r r 03756-030 to output amplifier figure 30. resistor string dac reference inputs there is a single reference input pin for the two dacs. the reference input is unbuffered. the user can have a reference voltage as low as 0.25 v and as high as v dd , because there is no restriction due to headroom and foot room of any reference amplifier. it is recommended to use a buffered reference in the external circuit, for example, ref192 . the input impedance is typically 45 k. output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 v to v dd when the reference is v dd . the amplifier is capable of driving a load of 2 k to gnd or v dd in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in figure 14 . the slew rate is 0.7 v/s with a half-scale settling time to 0.5 lsb (at 8 bits) of 6 s. power-on reset the ad5337/ad5338/ad5339 power on in a defined state via a power-on reset function. the power-on state is normal operation, with output voltage set to 0 v. both input and dac registers are filled with zeros until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering on.
ad5337/ad5338/ad5339 rev. c | page 16 of 28 serial interface the ad5337/ad5338/ad5339 are controlled via an i 2 c?- compatible serial bus. the dacs are connected to this bus as slave devices, that is, no clock is generated by the ad5337/ ad5338/ad5339 dacs. this interface is smbus compatible at v dd < 3.6 v. the ad5337/ad5338/ad5339 have a 7-bit slave address. the six msbs are 000110, and the lsb is determined by the state of the a0 pin. the facility of making hardwired changes to a0 allows the use of one or two of these devices on one bus. the ad5338-1 has a unique 7-bit slave address. the six msbs are 010001, and the lsb is determined by the state of the a0 pin. using a combination of ad5338 and ad5338-1 allows the user to accommodate four of these dual 10-bit devices (eight channels) on the same bus. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address, followed by an r/ w bit. (this bit determines whether data is read from or written to the slave device.) the slave with the address corresponding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits, followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read from or written to, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse, that is, the sda line remains high. the master then brings the sda line low before the 10th clock pulse and high during the 10 th clock pulse to establish a stop condition. read/write sequence for the ad5337/ad5338/ad5339, all write access sequences and most read sequences begin with the device address (with r/ w = 0), followed by the pointer byte. this pointer byte specifies which dac is being accessed in the subsequent read/write operation (see figure 31 ). in a write operation, the data follows immediately. in a read operation, the address is resent with r/ w = 1, and then the data is read back. however, it is also possible to perform a read operation by sending only the address with r/ w = 1. the previously loaded pointer settings are then used for the readback operation. see figure 32 for a graphical explanation of the interface. 0 x x lsb msb 0 dacb daca 00 03756-031 figure 31. pointer byte table 6 explains the individual bits that make up the pointer byte. table 6. pointer byte bits pointer byte bit description x dont care bits. 0 this bit is reserved and must be set to 0 dacb 1: the following data bytes are for dac b. daca 1: the following data bytes are for dac a. input shift register the input shift register is 16 bits wide. data is loaded into the device as two data bytes on the serial data line, sda, under the control of the serial clock input, scl. the timing diagram for this operation is shown in figure 2 . the two data bytes consist of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. the first two bits loaded are bit pd1 and bit pd0, which control the mode of operation of the device. see the power-down modes section for a complete description. bit 13 is clr , bit 12 is ldac , and the remaining bits are left- justified dac data bits, starting with the msb (see figure 32 ). table 7. input shift register register setting result clr 0 all dac registers and input registers are filled with 0s on completion of the write sequence. 1 normal operation. ldac 0 the two dac registers and, therefore, all dac outputs, simultaneously updated on completion of the write sequence. 1 addressed input register only is updated. there is no change in the contents of the dac registers.
ad5337/ad5338/ad5339 rev. c | page 17 of 28 default readback condition all pointer byte bits power up to 0. therefore, if the user initiates a readback without writing to the pointer byte first, no single dac channel has been specified. in this case, the default readback bits are all 0s, except for the clr bit, which is 1. multiple dac write sequence because there are individual bits in the pointer byte for each dac, it is possible to write the same data and control bits to two dacs simultaneously by setting the relevant bits to 1. multiple dac read back sequence if the user attempts to read back data from more than one dac at a time, the part reads back the default, power-on reset conditions, that is, all 0s except for clr , which is 1. write operation when writing to the ad5337/ad5338/ad5339 dacs, the user must begin with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte is followed by the pointer byte, which is also acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 33 . a stop condition follows. pd0 clr ldac d7 d6 d5 d4 pd1 lsb msb pd0 clr ldac d9 d8 d7 d6 pd1 pd0 d11 d10 d9 d8 pd1 most significant data byte 8-bit ad5337 lsb msb 10-bit ad5338 lsb msb 12-bit ad5339 clr ldac le a st significant data byte 8-bit ad5337 d3 d2 d1 d0 x d5 d4 d3 d2 d1 d0 x x d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb 10-bit ad5338 lsb msb 12-bit ad5339 xxx 03756-032 figure 32. data formats for write and read back 000 1 1x x scl sda scl sda 0 03756-033 start condition by master address byte a0 r/w msb most significant data byte lsb ack by ad533x msb ack by ad533x pointer byte lsb ack by ad533x msb least significant data byte lsb ack by ad533x stop condition by master figure 33. write sequence
ad5337/ad5338/ad5339 rev. c | page 18 of 28 read operation when reading data back from the ad5337/ad5338/ad5339 dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte is usually followed by the pointer byte, which is also acknowledged by the dac. then, the master initiates another start condition (repeated start) and the address is resent with r/ w = 1. this is acknowledged by the dac indicating that it is prepared to transmit data. two bytes of data are then read from the dac as shown in figure 34 . a stop condition follows. note that in a read sequence, data bytes are the same as those in the write sequence, except that dont cares are read back as 0s. however, if the master sends an ack and continues clocking scl (no stop is sent), the dac retransmits the same two bytes of data on sda. this allows continuous read back of data from the selected dac register. alternatively, the user can send a start followed by the address with r/ w = 1. in this case, the previously loaded pointer settings are used and read back of data can begin immediately. least significant data byte 000 11 x x scl sda scl sda 000 11 0 a0 scl sda 0 03756-034 start condition by master address byte a0 r/w msb ack by ad533x pointer byte lsb ack by ad533x address byte repeated start condition by master r/w ack by ad533x msb data byte lsb ack by master stop condition by master no ack by master lsb msb figure 34. read sequence
ad5337/ad5338/ad5339 rev. c | page 19 of 28 double-buffered interface the ad5337/ad5338/ad5339 dacs have a double-buffered interface consisting of two banks of registersan input register and a dac register per channel. the input register is directly connected to the input shift register, and the digital code is transferred to the relevant input register upon completion of a valid write sequence. the dac register contains the digital code used by the resistor string. access to the dac register is controlled by the ldac bit. when the ldac bit is set high, the dac register is latched and therefore, the input register can change state without affecting the dac register. this is useful if the user requires simultaneous updating of all dac outputs. the user can write to three of the input registers individually; by setting the ldac bit low when writing to the remaining dac input register, all outputs update simultaneously. these parts contain an extra feature whereby the dac register is only updated if its input register has been updated since the last time that ldac was brought low, thereby removing unnecessary digital crosstalk. power-down modes the ad5337/ad5338/ad5339 have very low power consumption, typically dissipating 0.75 mw with a 3 v supply and 1.5 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into one of three power-down modes, which are selected by bit 15 and bit 14 (pd1 and pd0) of the data byte. table 8 shows how the state of the bits corresponds to the mode of operation of the dac. table 8. pd1/pd0 operating modes pd1 pd0 operating mode 0 0 normal operation 0 1 power-down (1 k load to gnd) 1 0 power-down (100 k load to gnd) 1 1 power-down (three-state output) when both bits are 0, the dac works with its normal power consumption of 300 a at 5 v. however, for the three power- down modes, the supply current falls to 200 na at 5 v (80 na at 3 v). not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this is advantageous in that the output impedance of the part is known while the part is in power-down mode, which provides a defined input condition for whatever is connected to the output of the dac amplifier. there are three options. the output can be connected internally to gnd through a 1 k resistor, a 100 k resistor, or can be left open-circuited (three-state). resistor tolerance = 20%. the output stage is illustrated in figure 35 . amplifier v out 03756-035 resistor network power-down circuitry resistor string dac figure 35. output stage during power-down the bias generator, output amplifiers, resistor string, and all other associated linear circuitry are shut down when power- down mode is activated. however, the contents of the dac registers remain unchanged when power-down mode is activated. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from the rising edge of the eighth scl pulse to the time when the output voltage deviates from its power-down voltage (see figure 21 for a plot).
ad5337/ad5338/ad5339 rev. c | page 20 of 28 applications typical application circuit the ad5337/ad5338/ad5339 can be used with a wide range of reference voltages for full, one-quadrant multiplying capability over a reference range of 0 v to v dd . more typically, these devices are used with a fixed precision reference voltage. suitable references for 5 v operation are the ad780 , the ref192 , and the adr391 (2.5 v references). for 2.5 v operation, a suitable external reference would be the ad589 or ad1580 , a 1.23 v band gap reference. figure 36 shows a typical setup for the ad5337/ad5338/ad5339 when using an external reference. note that a0 can be high or low. gnd sda 0.1f refin a0 10f 1f scl v out a v out b 03756-036 v dd =2.5 v to 5.5 v ad780/ref192/adr391 with v dd =5v or ad589/ad1580 with v dd =2.5v ad5337/ ad5338/ ad5339 serial interface ext ref v in v out figure 36. ad5337/ad5338/ad5339 using external reference if an output range of 0 v to v dd is required, the simplest solution is to connect the reference input to v dd . because this supply can be inaccurate and noisy, the ad5337/ad5338/ ad5339 can be powered from a reference voltage, for example, using a 5 v reference such as the ref195 , which provides a steady output supply voltage. with no load on the dacs, the ref195 is required to supply 600 a supply current to the dac and 112 a to the reference input. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads; therefore, the total current required with a 10 k load on each output is 712 a 2 (5 v/10 k ) = 1.7 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 3.4 ppm (17 v) for the 1.7 ma current drawn from it. this corresponds to a 0.0009 lsb error at 8 bits and a 0.014 lsb error at 12 bits. bipolar operation the ad5337/ad5338/ad5339 are designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 37 . this circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. +5v ?5v 10f 6v to 12v ad5339 0.1f r1 = 10k ? 5v r2 = 10k ? a0 g n d ad1585 + 5 v g n d 1 f 03756-037 a d 8 2 0 / o p 2 9 5 2 - w i r e s e r i a l i n t e r f a c e s d a s c l r e f i n v out b v out a v dd v out v in figure 37. bipolar operation with the ad5339 the output voltage for any input code can be calculated as follows: u u u r1 r2 refin r1 r2r1d refin v n out 2 where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. with refin = 5 v, r1 = r2 = 10 k: v out = (10 d /2 n ) ? 5 multiple devices on one bus figure 38 shows two ad5339 devices on the same serial bus. each has a different slave address because the state of the a0 pin is different. this allows each of four dacs to be written to or read from independently. pull-up resistors scl sda ad5339 a0 ad5339 scl sda a0 v dd microcontroller 03756-038 figure 38. multiple ad5339 devices on one bus
ad5337/ad5338/ad5339 rev. c | page 21 of 28 product as a digi tally programmable window detector figure 39 shows a digitally programmable upper/lower limit detector using the two dacs in the ad5337/ad5338/ad5339. the upper and lower limits for the test are loaded into dac a and dac b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led indicates the fail condition. 5 v gnd refin pass/fail 1/6 74hc05 fail pass 1k? 0.1f scl sda scl din 1k? 10f 03756-039 v ref v in 1 additional pins omitted for clarity. ad5337/ ad5338/ ad5339 1 v dd v out a v out b 1/2 cmp04 figure 39. window detection coarse and fine adjustment capabilities the two dacs in the ad5337/ad5338/ad5339 can be paired together to form a coarse and fine adjustment function, as shown in figure 40 . dac a is used to provide the coarse adjustment while dac b provides the fine adjustment. varying the ratio of r1 and r2 changes the relative effect of the coarse and fine adjustments. with the resistor values and external reference shown, the output amplifier has unity gain for the dac a output, thus, the output range is 0 v to 2.5 v ? 1 lsb. for dac b, the amplifier has a gain of 7.6 10 C3 , giving dac b a range equal to 19 mv. the circuit is shown with a 2.5 v reference, but reference voltages up to v dd can be used. the op amps indicated allow a rail-to-rail output swing. 1f refin gnd v out b 0.1f 10f v out gnd 5v 0 3756-040 v out ad820/ op295 r1 390 ? r2 51.2k ? 1 additional pins omitted for clarity. v dd =5 v ext ref v in v out a v dd ad5337/ ad5338/ ad5339 1 r4 390 ? r3 51.2k ? ad780/ref192/adr391 with v dd =5v figure 40. coarse/fine adjustment power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5337/ad5338/ad5339 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5337/ad5338/ad5339 are in a system where multiple devices require an agnd-to- dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5337/ad5338/ad5339 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) to provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5337/ad5338/ad5339 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. a ground line routed between the sda and scl lines helps to reduce crosstalk between them. this is not required on a multilayer board because there is a separate ground plane, but separating the lines does help. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. using a microstrip technique is the best solution, but its use is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side.
ad5337/ad5338/ad5339 rev. c | page 22 of 28 table 9. overview of all ad53xx serial devices part no. resolution (bits) no. of dacs dnl (lsbs) interface settling time (s) package no. of pins single ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.50 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.00 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.50 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.00 2-wire 8 sot-23, msop 6, 8 dual ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.50 spi 7 msop 8 ad5322 12 2 1.00 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.50 spi 7 tssop 16 ad5323 12 2 1.00 spi 8 tssop 16 ad5337 8 2 0.25 2-wire 6 msop 8 ad5338 10 2 0.50 2-wire 7 msop 8 ad5338-1 10 2 0.50 2-wire 7 msop 8 ad5339 12 2 1.00 2-wire 8 msop 8 quad ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.50 spi 7 msop 10 ad5324 12 4 1.00 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.50 2-wire 7 msop 10 ad5325 12 4 1.00 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.50 2-wire 7 tssop 16 ad5326 12 4 1.00 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.50 spi 7 tssop 16 ad5327 12 4 1.00 spi 8 tssop 16 octal ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.50 spi 7 tssop 16 ad5328 12 8 1.00 spi 8 tssop 16
ad5337/ad5338/ad5339 rev. c | page 23 of 28 table 10. overview of ad53xx parallel devices additional pin functions part no. resolution (bits) dnl (lsbs) no. of v ref pins settling time (s) buf gain hben clr package no. of pins single ad5300 8 0.25 1 6 * * * tssop 20 ad5331 10 0.50 1 7 * * tssop 20 ad5340 12 1.00 1 8 * * * tssop 24 ad5341 12 1.00 1 8 * * * * tssop 20 dual ad5332 8 0.25 2 6 * tssop 20 ad5333 10 0.50 2 7 * * * tssop 24 ad5342 12 1.00 2 8 * * * tssop 28 ad5343 12 1.00 1 8 * * tssop 20 quad ad5334 8 0.25 2 6 * * tssop 24 ad5335 10 0.50 2 7 * * tssop 24 ad5336 10 0.50 4 7 * * tssop 28 ad5344 12 1.00 4 8 tssop 28 octal ad5346 8 0.25 4 6 * * * tssop, lfcsp 38, 40 ad5347 10 0.50 4 7 * * * tssop, lfcsp 38, 40 ad5348 12 1.00 4 8 * * * tssop, lfcsp 38, 40
ad5337/ad5338/ad5339 rev. c | page 24 of 28 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 41. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model temperature range package description package option branding ad5337arm ?40c to +105c 8-lead msop rm-8 d23 ad5337arm-reel7 ?40c to +105c 8-lead msop rm-8 d23 ad5337armz 1 ?40c to +105c 8-lead msop rm-8 d23# ad5337armz-reel7 1 ?40c to +105c 8-lead msop rm-8 d23# ad5337brm-reel ?40c to +105c 8-lead msop rm-8 d20 ad5337brm-reel7 ?40c to +105c 8-lead msop rm-8 d20 ad5337brmz 1 ?40c to +105c 8-lead msop rm-8 d20# ad5337brmz-reel 1 ?40c to +105c 8-lead msop rm-8 d20# ad5337brmz-reel7 1 ?40c to +105c 8-lead msop rm-8 d20# ad5338arm ?40c to +105c 8-lead msop rm-8 d24 ad5338armz 1 ?40c to +105c 8-lead msop rm-8 d5f ad5338armz-reel7 1 ?40c to +105c 8-lead msop rm-8 d5f ad5338armz-1 1 ?40c to +105c 8-lead msop rm-8 d57 ad5338armz-1reel7 1 ?40c to +105c 8-lead msop rm-8 d57 ad5338brm ?40c to +105c 8-lead msop rm-8 d21 ad5338brm-reel ?40c to +105c 8-lead msop rm-8 d21 ad5338brm-reel7 ?40c to +105c 8-lead msop rm-8 d21 ad5338brmz 1 ?40c to +105c 8-lead msop rm-8 d5h ad5338brmz-1 1 ?40c to +105c 8-lead msop rm-8 d58 ad5338brmz-1reel7 1 ?40c to +105c 8-lead msop rm-8 d58 ad5339arm ?40c to +105c 8-lead msop rm-8 d25 ad5339armz 1 ?40c to +105c 8-lead msop rm-8 d6p AD5339ARMZ-REEL7 1 ?40c to +105c 8-lead msop rm-8 d6p ad5339brm ?40c to +105c 8-lead msop rm-8 d22 ad5339brm-reel ?40c to +105c 8-lead msop rm-8 d22 ad5339brm-reel7 ?40c to +105c 8-lead msop rm-8 d22 ad5339brmz 1 ?40c to +105c 8-lead msop rm-8 d6r ad5339brmz-reel 1 ?40c to +105c 8-lead msop rm-8 d6r ad5339brmz-reel7 1 ?40c to +105c 8-lead msop rm-8 d6r 1 z = rohs compliant part. # denotes lead-free product may be top or bottom marked.
ad5337/ad5338/ad5339 rev. c | page 25 of 28 notes
ad5337/ad5338/ad5339 rev. c | page 26 of 28 notes
ad5337/ad5338/ad5339 rev. c | page 27 of 28 notes
ad5337/ad5338/ad5339 rev. c | page 28 of 28 notes purchase of licensed i2c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips . ?2003C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03756-0-9/07(c)

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